#SPI
set_property PACKAGE_PIN F18 [get_ports spi0_csn]
set_property IOSTANDARD LVCMOS25 [get_ports spi0_csn]
set_property PULLUP true [get_ports spi0_csn]
set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports spi0_clk]
set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25} [get_ports spi0_mosi]
set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25} [get_ports spi0_miso]

#REST
set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS25} [get_ports gpio_resetb]


# DATA INTERFACE
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports rx_clk_in_p]
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports rx_clk_in_n]
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports rx_frame_in_p]
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports rx_frame_in_n]
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {rx_data_in_p[0]}]
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {rx_data_in_n[0]}]
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {rx_data_in_p[1]}]
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {rx_data_in_n[1]}]
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {rx_data_in_p[2]}]
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {rx_data_in_n[2]}]
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {rx_data_in_p[3]}]
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {rx_data_in_n[3]}]
set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {rx_data_in_p[4]}]
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {rx_data_in_n[4]}]
set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {rx_data_in_p[5]}]
set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {rx_data_in_n[5]}]
set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports tx_clk_out_p]
set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports tx_clk_out_n]
set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports tx_frame_out_p]
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports tx_frame_out_n]
set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {tx_data_out_p[0]}]
set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {tx_data_out_n[0]}]
set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {tx_data_out_p[1]}]
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {tx_data_out_n[1]}]
set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {tx_data_out_p[2]}]
set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {tx_data_out_n[2]}]
set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {tx_data_out_p[3]}]
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {tx_data_out_n[3]}]
set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {tx_data_out_p[4]}]
set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {tx_data_out_n[4]}]
set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {tx_data_out_p[5]}]
set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports {tx_data_out_n[5]}]

#PINCTL ENSM INTERFACE
set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports enable]
set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25} [get_ports txnrx]

###############################################################################
# LVDS Interface
###############################################################################
# Radio clock from 9022 max inteaval 120mhz   = 0.009us = 9ns
create_clock -period 10.000 -name m_clk [get_ports rx_clk_in_p]
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks m_clk]
set_false_path -from [get_clocks m_clk] -to [get_clocks clk_fpga_0]

#create_clock -period 20.000 -name sample_clk -waveform {0.000 8.000} [get_pins core_i/design_2_lvds_test_i/lvds_0/adc_valid]
#set_false_path -from [get_clocks sample_clk] -to [get_clocks clk_fpga_0]
#set_input_delay -clock [get_clocks m_clk] -max 2 [get_ports {{rx_data_in_p[0]} {rx_data_in_p[1]} {rx_data_in_p[2]} {rx_data_in_p[3]} {rx_data_in_p[4]} {rx_data_in_p[5]} rx_frame_in_p}]
#set_input_delay -clock [get_clocks m_clk] -min 0 [get_ports {{rx_data_in_p[0]} {rx_data_in_p[1]} {rx_data_in_p[2]} {rx_data_in_p[3]} {rx_data_in_p[4]} {rx_data_in_p[5]} rx_frame_in_p}]

#create_clock -period 50.000 -name m_clk_loop [get_ports tx_clk_out_p]
#set_false_path -from [get_clocks m_clk] -to [get_clocks m_clk_loop]
#set_output_delay -clock [get_clocks m_clk_loop] 0.000 [get_ports {{tx_data_out_p[0]} {tx_data_out_p[1]} {tx_data_out_p[2]} {tx_data_out_p[3]} {tx_data_out_p[4]} {tx_data_out_p[5]} tx_frame_out_p}]









